| 1 |
23/9/13 |
Class Introduction [slides] |
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| 2 |
23/9/20 |
Advanced HDL basics & Timing [slides] |
FSM Templates:1, 2 |
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| 3 |
23/9/27 |
Logic Synthesis - I [slides] |
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| 4 |
23/10/4 |
Happy holiday😃 |
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| 5 |
23/10/11 |
Logic Synthesis - II |
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assignment1, due 23:59:00, 11/1/2023 |
| 6 |
23/10/18 |
Data Formats & Circuits [slides] |
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| 7 |
23/10/25 |
Memory [slides] Technologies |
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| 8 |
23/11/1 |
CPU Microarchitecture [slides] Lab |
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| 9 |
23/11/8 |
CPU Microarchitecture (conti.) [slides] |
MinimalistCPU |
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| 10 |
23/11/15 |
Instrumentalism Intro of DNN - I[slides] |
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| 11 |
23/11/22 |
Systolic Array [slides] |
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| 12 |
23/11/29 |
Processing-in-Memory [slides] & Progress Report - I |
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| 13 |
23/12/6 |
Latest Hardware Design Languages [slides] & Lab Time |
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| 14 |
23/12/13 |
Progress Report - I |
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| 15 |
23/12/20 |
Lab Time |
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| 16 |
23/12/27 |
Final Presentation - Progress Report II |
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| 17 |
24/1/3 |
[Final Exam Week] No Lecture |
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