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COURSE INFORMATION

AGENDA

Week Date Lecture Reference Assignment
1 9/11 Class Introduction [slides] Verilog HDL 2005 Standard [doc]  
2 9/18 Advanced HDL basics & Timing [slides] FSM Templates:1, 2  
3 9/25 Logic Synthesis ([slides]) - I    
4 10/2 Happy holiday😃    
5 10/9 Logic Synthesis - II    
6 10/16 Data Formats & Circuits ([slides]    
7 10/23 Data Formats & Circuits (conti.)    
8 10/30 Memory Technologies ([slides]    
9 11/6 Memory (conti.) assignment, due 23:59:00, 12/8/2024  
10 11/13 CPU Microarchitecture [slides]    
11 11/20 Systolic Array [slides] Project Guide  
12 11/27(出差,挪到12月6日上午9am-12pm)    
13 12/4 Two Examples for Programmable AI Chip (slides) & Discussion Time MinimalistCPU, PUMA  
13 12/6 Progress Report - I & Lab Time    
14 12/11 Instrumentalism Intro of Latest Machine Learning & Lab Time    
15 12/18 Latest Hardware Design Languages & Lab Time    
16 12/25 Final Presentation - Progress Report II (the last lecture)    
19 Jan 13 11:59:00,2025 (tentative) Final Project Submission [Final Exam Week] No Lecture    

USEFUL TOOLS

GRADE BREAKDOWN