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COURSE INFORMATION

AGENDA

Week Date Lecture Reference Assignment
1 9/11 Class Introduction [slides] Verilog HDL 2005 Standard [doc]  
2 9/18 Advanced HDL basics & Timing [slides] FSM Templates:1, 2  
3 9/25 Logic Synthesis - I    
4 10/2 Happy holiday😃    
5 10/9 Logic Synthesis - II   assignment1, due 23:59:00, 11/5/2024
6 10/16 Data Formats & Circuits    
7 10/23 Memory Technologies    
8 10/30 CPU Microarchitecture Lab    
9 11/6 CPU Microarchitecture (conti.) MinimalistCPU  
10 11/13 Instrumentalism Intro of DNN - I    
11 11/20 Systolic Array    
12 11/27 Processing-in-Memory & Progress Report - I    
13 12/4 Latest Hardware Design Languages & Lab Time    
14 12/11 Progress Report - I    
15 12/18 Lab Time    
16 12/25 Final Presentation - Progress Report II    
17 25/1/1 [Final Exam Week] No Lecture    

USEFUL TOOLS

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