| 1 |
9/10 |
Class Introduction [slides] |
Verilog HDL 2005 Standard [doc] |
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| 2 |
9/17 |
Advanced HDL basics & Timing |
FSM Templates:1, 2 |
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| 3 |
9/24 |
Latest AI Chip Architectures |
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| 4 |
10/1 |
Happy holiday😃 |
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| 5 |
10/8 |
Happy holiday😃 |
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| 6 |
10/15 |
TPU vs GPU (Paper1, Paper2, Code1) |
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| 7 |
10/22 |
Neuromorphic Computer (Paper1, Paper2, Paper3) |
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| 8 |
10/29 |
CNN ASICs (Paper1, Paper2, Code1) |
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| 9 |
11/5 |
RISC-V for AI (Paper1, Paper2, Code1) |
assignment (设计架构框图，分工接口表) due 23:59:00, 11/26/2025，每组提交至微信群 |
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| 10 |
11/12 |
Dataflow (Paper1, Paper2, Historical View) |
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| 11 |
11/19 |
Wafer-scale Architectures (Paper1, Paper2 Cerebras Chip 123) |
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| 12 |
11/26 |
Processing-In-Memory (RRAM PIM, DRAM PIM SW,DRAM PIM Primer, Code APIM & DPIM) |
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| 13 |
12/3 |
LLM Accelerator (Comprehensive Review, Paper2) |
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| 14 |
12/10 |
Optical Communications & Computing (Paper1, Paper2) |
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| 15 |
12/17 |
Quantum AI Computing (Basics, Paper1, Paper2) |
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| 16 |
12/24 |
Final Presentation |
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| 19 |
Jan 13 11:59:00,2025 (tentative) Final Project Submission |
[Final Exam Week] No Lecture |
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