Behavioral Models

Description

This step build memories, including RAM (random-access memory) and ROM (read-only memory to store all instructions/programs).

The design is in embark-rv/src/00_memory/rtl/.Testbench is provided in embark-rv/src/00_memory/test/

Verilog Behavioral Models

Please download: [here]

Chisel Behavioral Models

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C++ Behavioral Models

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