1 |
9/14 |
Class Introduction & Why AI ASIC? |
[slides] |
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2 |
9/21 |
Introduction to Verilog HDL |
[slides], [handout] |
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3 |
9/28 |
Introduction to Verilog HDL-II |
Verilog_Examples(see “makefile”) |
assignment1 |
4 |
10/5 |
Happy holiday! 😆 No Lecture |
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5 |
10/12 |
Single-Core CPU |
[slides], [minimalCPU], Verilog_Example_v2 |
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6 |
10/19 |
Single-Core CPU-2 |
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7 |
10/26 |
Assembly Tutorial 1 |
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8 |
11/2 |
GPU Array-I |
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9 |
11/9 |
Systolic Array-II |
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10 |
11/16 |
Design Flow - 1 |
[slides] [Lab1] [Unified_multiport_RAM] |
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11 |
11/23 |
Design Flow -2 [slides] |
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12 |
11/30 |
Lab-1 Practice |
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13 |
12/7 |
AI for Chips: Introduction |
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14 |
12/14 |
🌟Lab 2 AI for Chip |
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15 |
12/21 |
Continue Lab 3 |
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16 |
12/28 |
Paper Sharing Presentation |
[paper candidates] |
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