Works

Toolkits

• PIM-Gym: PIM macro Verilog/Chisel behavioral models & examples of integrating PIM into SoC
  • https://bonany.cc/pim-gym/
• AttentionLego: vanilla self-attention block for large language model accelerators
  • https://bonany.cc/attentionlego/
• PISLB: open-source PIM macro Verilog/Chisel behavioral model library
  • https://bonany.gitlab.io/pis/
• Pyjuice: prbabilistic circuits【collaboration with UCLA】
  • https://github.com/Juice-jl/pyjuice

Chip Gallery

SRAM & RRAM Compute-In-Memory Chips Made by Our Research Group (2020~now)