| 1 |
9/11 |
Class Introduction [slides] |
Verilog HDL 2005 Standard [doc] |
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| 2 |
9/18 |
Advanced HDL basics & Timing [slides] |
FSM Templates:1, 2 |
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| 3 |
9/25 |
Logic Synthesis ([slides]) - I |
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| 4 |
10/2 |
Happy holiday😃 |
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| 5 |
10/9 |
Logic Synthesis - II |
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| 6 |
10/16 |
Data Formats & Circuits ([slides] |
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| 7 |
10/23 |
Data Formats & Circuits (conti.) |
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| 8 |
10/30 |
Memory Technologies ([slides] |
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| 9 |
11/6 |
Memory (conti.) |
assignment, due 23:59:00, 12/8/2024 |
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| 10 |
11/13 |
CPU Microarchitecture [slides] |
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| 11 |
11/20 |
Systolic Array [slides] |
Project Guide |
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| 12 |
11/27(出差,挪到12月6日上午9am-12pm) |
Progress Report - I & Instrumentalism Intro of DNN |
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| 13 |
12/4 |
Latest Hardware Design Languages & Lab Time |
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| 14 |
12/11 |
Progress Report - I |
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| 15 |
12/18 |
Lab Time |
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| 16 |
12/25 |
Final Presentation - Progress Report II |
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| 17 |
25/1/1 |
[Final Exam Week] No Lecture |
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